Electronic systems are becoming increasingly more complex and operate at clock rates that have increasingly higher speeds. As the complexities and clock rates of an electronic system increase, clock signals of the electronic system may experience substantial phase shifts as they travel from one block of the electronic system to another block of the electronic system. The differences in phase of the clock signals received by different blocks may lead to loss of data and errors.
Clock trees and delay-lock loops (DLLs) have been traditionally used to synchronize clock signals received by different blocks. However, clock trees and DLLs require a substantial amount of power and hardware to implement. Further, clock trees and DLLs may be difficult to implement.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one example technology area where some embodiments described herein may be practiced.